US 12,364,033 B2
Semiconductor device and method of manufacturing semiconductor device
Hajime Watakabe, Tokyo (JP); Akihiro Hanada, Tokyo (JP); Marina Mochizuki, Tokyo (JP); Ryo Onodera, Tokyo (JP); Fumiya Kimura, Tokyo (JP); and Isao Suzumura, Tokyo (JP)
Assigned to JAPAN DISPLAY INC., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Nov. 21, 2023, as Appl. No. 18/515,288.
Application 18/515,288 is a division of application No. 17/167,081, filed on Feb. 4, 2021, granted, now 11,855,117.
Claims priority of application No. 2020-025023 (JP), filed on Feb. 18, 2020.
Prior Publication US 2024/0088192 A1, Mar. 14, 2024
Int. Cl. H10F 39/18 (2025.01); H10F 39/00 (2025.01)
CPC H10F 39/18 (2025.01) [H10F 39/014 (2025.01); H10F 39/8033 (2025.01); H10F 39/811 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device comprising the steps of:
forming a first organic insulating film on a substrate;
selectively forming a cathode electrode on the first organic insulating film;
forming an N+ layer so as to cover an upper portion of the first organic insulating film and the cathode electrode;
forming an I layer so as to cover the N+ layer;
forming a P+ layer so as to cover the I layer;
executing boron ion implantation on the P+ layer after the formation of the P+ layer;
selectively forming a resist film on the P+ layer; and
executing dry etching on the P+ layer, the I layer, and the N+ layer using the resist film as a mask.