US 12,364,024 B2
Solar cell, method for preparing same and solar cell module
Wenqi Li, Zhejiang (CN); Peiting Zheng, Zhejiang (CN); Jie Yang, Zhejiang (CN); Menglei Xu, Zhejiang (CN); Xinyu Zhang, Zhejiang (CN); and Hao Jin, Zhejiang (CN)
Assigned to SHANGHAI JINKO GREEN ENERGY ENTERPRISE MANAGEMENT CO., LTD., Shanghai (CN); and ZHEJIANG JINKO SOLAR CO., LTD., Haining (CN)
Filed by SHANGHAI JINKO GREEN ENERGY ENTERPRISE MANAGEMENT CO., LTD., Shanghai (CN); and ZHEJIANG JINKO SOLAR CO., LTD., Zhejiang (CN)
Filed on Aug. 11, 2023, as Appl. No. 18/448,847.
Application 18/448,847 is a continuation of application No. 17/504,498, filed on Oct. 18, 2021, granted, now 11,784,266.
Claims priority of application No. 202111064317.8 (CN), filed on Sep. 10, 2021.
Prior Publication US 2023/0420589 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10F 19/80 (2025.01); H10F 71/00 (2025.01); H10F 77/30 (2025.01); H10F 77/70 (2025.01)
CPC H10F 19/80 (2025.01) [H10F 71/128 (2025.01); H10F 71/129 (2025.01); H10F 77/311 (2025.01); H10F 77/707 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A solar cell, comprising:
a substrate having a front surface and a back surface opposite to the front surface;
a first passivation layer formed over the front surface of the substrate, a second passivation layer formed over the first passivation layer, and a third passivation layer formed over the second passivation layer; wherein the first passivation layer includes a dielectric material; the second passivation layer includes a first SiuNv material, wherein v/u is in the range of 1.3 to 1.7; and the third passivation layer includes a SirOs material, and wherein s/r is in the range of 1.9 to 3.2, wherein the third passivation layer includes a first silicon oxide sub-layer formed over the second passivation layer, a second silicon oxide sub-layer formed over the first silicon oxide sub-layer, and a third silicon oxide sub-layer formed over the second silicon oxide sub-layer, wherein in a direction perpendicular to the front surface, the first silicon oxide sub-layer has a thickness in a range of 10 nm to 20 nm, the second silicon oxide sub-layer has a thickness in a range of 20 nm to 30 nm, and the third silicon oxide sub-layer has a thickness in a range of 30 nm to 40 nm; and
a tunneling oxide layer formed over the back surface of the substrate and a doped conductive layer formed over the tunneling oxide layer.