US 12,364,023 B2
Semiconductor devices with improved layout to increase electrostatic discharge performance
Hsiao-Ching Huang, New Taipei (TW); Hao-Hua Hsu, Taipei (TW); and Sheng-Fu Hsu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 3, 2022, as Appl. No. 17/831,717.
Prior Publication US 2023/0395592 A1, Dec. 7, 2023
Int. Cl. H10D 89/60 (2025.01); H02H 9/04 (2006.01)
CPC H10D 89/819 (2025.01) [H02H 9/046 (2013.01); H10D 89/911 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a first semiconductor device disposed on a semiconductor substrate, wherein the first semiconductor device comprises a first gate structure, a first source region, and a first drain region, wherein the first source region and the first drain region are disposed in a first well region, wherein the first well region comprises a first doping type and the first source and drain regions comprise a second doping type opposite the first doping type;
a second semiconductor device disposed on the semiconductor substrate, wherein the second semiconductor device comprises a second gate structure, a second source region, and a second drain region, wherein the second source region and the second drain region are disposed in a second well region, wherein the second well region comprises the first doping type and the second source and drain regions comprise the second doping type, wherein the first well region is laterally offset from the second well region by a first distance; and
a third well region disposed in the semiconductor substrate and laterally between the first and second well regions, wherein the third well region comprises the second doping type, wherein the third well region continuously laterally extends along the first distance and abuts bottoms of the first well region and the second well region.