| CPC H10D 89/611 (2025.01) [H10D 8/043 (2025.01); H10D 8/411 (2025.01); H10D 62/126 (2025.01)] | 20 Claims |
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1. A method for forming an integrated chip, the method comprising:
forming an isolation structure within a semiconductor substrate;
forming a gate structure over the semiconductor substrate, wherein the gate structure comprises a gate electrode overlying a gate dielectric layer, wherein a thickness of the gate dielectric layer is about 140 Angstroms or greater;
forming a well region within the semiconductor substrate, wherein the well region has a first doping type and is formed through an opening defined by sidewalls of the gate structure;
forming a first contact region within the well region, wherein the first contact region is formed through the opening and comprises a second doping type opposite the first doping type; and
forming a second contact region and a third contact region on opposite sides of the gate electrode, wherein the second and third contact regions respectively comprise the first doping type.
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