US 12,364,017 B2
Semiconductor structure, electronic device, and method of manufacturing semiconductor structure
I-Sheng Chen, Taipei (TW); Yi-Jing Li, Hsinchu (TW); Chia-Ming Hsu, Hualien County (TW); Wan-Lin Tsai, Hsinchu (TW); and Clement Hsingjen Wann, Carmel, NY (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Feb. 21, 2024, as Appl. No. 18/583,756.
Application 18/583,756 is a continuation of application No. 17/351,240, filed on Jun. 18, 2021, granted, now 11,942,467.
Prior Publication US 2024/0194663 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 86/85 (2025.01); H01L 21/70 (2006.01); H10D 1/68 (2025.01)
CPC H10D 86/85 (2025.01) [H01L 21/707 (2013.01); H10D 1/692 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first metal-dielectric-metal layer, comprising:
a plurality of first fingers and a plurality of second fingers arranged in parallel and staggeredly; and
a first dielectric material between the first fingers and the second fingers;
a first dielectric layer over the first metal-dielectric-metal layer;
a first conductive layer over the first dielectric layer;
a second conductive layer over the first conductive layer; and
a second dielectric layer between the first conductive layer and the second conductive layer;
wherein one of the first fingers is connected to a first voltage at a first terminal which electrically connects to an anode of a diode, and the diode includes at least one of a laser diode, a CMOS image sensor (CIS) pixel unit, an OLED pixel unit, or a combination thereof; and
wherein the second conductive layer or one of the second fingers is connected to a second terminal which is configured to receive a second voltage lower than the first voltage at the first terminal.