US 12,364,004 B2
Dummy fin contact in vertically stacked transistors
Joshua M. Rubin, Albany, NY (US); Chen Zhang, Guilderland, NY (US); Tenko Yamashita, Schenectady, NY (US); and Brent A Anderson, Jericho, VT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jun. 23, 2022, as Appl. No. 17/847,765.
Prior Publication US 2023/0420458 A1, Dec. 28, 2023
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01)
CPC H10D 84/856 (2025.01) [H10D 30/031 (2025.01); H10D 30/6728 (2025.01); H10D 30/6729 (2025.01); H10D 64/62 (2025.01); H10D 84/0186 (2025.01); H10D 84/0195 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A plurality of transistor components, wherein the plurality of transistor components comprises:
a first bottom transistor, wherein the first bottom transistor comprises a channel, a gate, a source, and a drain;
a first dummy fin contact on top of the first bottom transistor, wherein the first dummy fin contact is proximately connected to the first bottom transistor, and the first dummy fin contact replaces a portion of a first top transistor, wherein the first top transistor is a dummy transistor; and
a first set of stacked transistors, wherein the first set of stacked transistors comprises a second top transistor on top of a second bottom transistor.