US 12,363,982 B2
Integrated circuit layouts with source and drain contacts of different widths
Shang-Syuan Ciou, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Jung-Chan Yang, Hsinchu (TW); and Li-Chun Tien, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 18, 2022, as Appl. No. 17/698,857.
Application 17/698,857 is a division of application No. 16/580,779, filed on Sep. 24, 2019, granted, now 11,302,787.
Claims priority of provisional application 62/753,460, filed on Oct. 31, 2018.
Prior Publication US 2022/0208976 A1, Jun. 30, 2022
Int. Cl. H10D 64/23 (2025.01); H10D 30/60 (2025.01); H10D 62/13 (2025.01)
CPC H10D 64/254 (2025.01) [H10D 30/601 (2025.01); H10D 62/149 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A system for processing a layout of a semiconductor device, comprising:
at least one processor; and
a computer readable storage medium connected to the at least one processor, wherein the at least one processor is configured to execute instructions stored on the computer readable storage medium to:
generate an active region layout pattern extending in a first direction,
generate a plurality of gate layout patterns extending in a second direction different from the first direction, wherein the plurality of gate layout patterns extends across the active region layout pattern;
generate a plurality of source/drain region layout patterns in the active region layout pattern on opposite sides of the plurality of gate layout patterns;
generate a plurality of source/drain contact layout patterns overlapping the plurality of source/drain region layout patterns; and
generate one or more mark layers, wherein each of one or more mark layers labels a corresponding source/drain contact layout pattern of the plurality of source/drain contact layout patterns and is usable to indicate the corresponding source/drain layout pattern of the plurality of source/drain contact layout patterns has a width greater than each source/drain layout pattern of the plurality of source/drain contact layout patterns that is not labeled by the one or more mark layers.