US 12,363,978 B2
Field effect transistor with negative capacitance dielectric structures
Chansyun David Yang, Shinchu (TW); Keh-Jeng Chang, Shinchu (TW); and Chan-Lon Yang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,261.
Application 17/409,195 is a division of application No. 16/573,334, filed on Sep. 17, 2019, granted, now 11,114,547, issued on Sep. 7, 2021.
Application 18/362,261 is a continuation of application No. 18/175,180, filed on Feb. 27, 2023, granted, now 11,791,397.
Application 18/175,180 is a continuation of application No. 17/409,195, filed on Aug. 23, 2021, granted, now 11,594,616, issued on Feb. 28, 2023.
Prior Publication US 2024/0021705 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 64/01 (2025.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/00 (2025.01); H10D 64/68 (2025.01)
CPC H10D 64/018 (2025.01) [H10D 30/0243 (2025.01); H10D 30/6212 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 62/116 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/118 (2025.01); H10D 64/691 (2025.01); H01L 21/02181 (2013.01); H01L 21/0228 (2013.01); H01L 21/3065 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a plurality of semiconductor layers on a substrate; and
forming a spacer structure between end portions of the plurality of semiconductor layers, wherein the spacer structure comprises:
a negative capacitance (NC) dielectric layer comprising an NC dielectric material;
a non-NC dielectric structure comprising a low-k dielectric material; and
an air gap in contact with the NC dielectric layer and the non-NC dielectric layer.