US 12,363,969 B2
Passivation layer for epitaxial semiconductor process
Yin-Kai Liao, Taipei (TW); Sin-Yi Jiang, Hsinchu (TW); Hsiang-Lin Chen, Hsinchu (TW); Yi-Shin Chu, Hsinchu (TW); Po-Chun Liu, Hsinchu (TW); Kuan-Chieh Huang, Hsinchu (TW); Jyh-Ming Hung, Dacun Township (TW); and Jen-Cheng Liu, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jan. 5, 2024, as Appl. No. 18/405,099.
Application 17/869,885 is a division of application No. 17/036,287, filed on Sep. 29, 2020, granted, now 11,508,817, issued on Nov. 22, 2022.
Application 18/405,099 is a continuation of application No. 17/869,885, filed on Jul. 21, 2022, granted, now 11,908,900.
Claims priority of provisional application 63/030,980, filed on May 28, 2020.
Prior Publication US 2024/0136401 A1, Apr. 25, 2024
Int. Cl. H10D 62/17 (2025.01); H10D 30/01 (2025.01); H10D 62/834 (2025.01); H10D 64/66 (2025.01)
CPC H10D 62/378 (2025.01) [H10D 30/0227 (2025.01); H10D 62/834 (2025.01); H10D 64/663 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a substrate comprising a first semiconductor material;
a second semiconductor material disposed on the first semiconductor material;
a passivation layer disposed on the second semiconductor material;
a first doped region and a second doped region extending through a part of the passivation layer and into a part of the second semiconductor material; and
a silicide arranged between interior sidewalls of the passivation layer and along tops of the first doped region and the second doped region.