US 12,363,967 B2
Integration methods to fabricate internal spacers for nanowire devices
Seiyon Kim, Portland, OR (US); Kelin J. Kuhn, Aloha, OR (US); Tahir Ghani, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Mark Armstrong, Portland, OR (US); Rafael Rios, Portland, OR (US); Abhijit Jayant Pethe, Hillsboro, OR (US); and Willy Rachmady, Beaverton, OR (US)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by Sony Group Corporation, Tokyo (JP)
Filed on Nov. 30, 2023, as Appl. No. 18/525,609.
Application 15/333,123 is a division of application No. 13/539,195, filed on Jun. 29, 2012, granted, now 9,484,447, issued on Nov. 1, 2016.
Application 18/525,609 is a continuation of application No. 17/703,218, filed on Mar. 24, 2022, granted, now 11,869,939.
Application 17/703,218 is a continuation of application No. 17/013,449, filed on Sep. 4, 2020, granted, now 11,302,777, issued on Apr. 12, 2022.
Application 17/013,449 is a continuation of application No. 16/740,132, filed on Jan. 10, 2020, granted, now 10,804,357, issued on Oct. 13, 2020.
Application 16/740,132 is a continuation of application No. 16/358,613, filed on Mar. 19, 2019, granted, now 10,580,860, issued on Jul. 11, 2019.
Application 16/358,613 is a continuation of application No. 16/153,456, filed on Oct. 5, 2018, granted, now 10,283,589, issued on May 7, 2019.
Application 16/153,456 is a continuation of application No. 15/859,226, filed on Dec. 29, 2017, granted, now 10,121,856, issued on Nov. 6, 2018.
Application 15/859,226 is a continuation of application No. 15/333,123, filed on Oct. 24, 2016, granted, now 9,859,368, issued on Jan. 2, 2018.
Prior Publication US 2024/0153995 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 62/10 (2025.01); B82Y 40/00 (2011.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/3115 (2006.01); H10D 30/60 (2025.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01)
CPC H10D 62/121 (2025.01) [H01L 21/30604 (2013.01); H01L 21/3105 (2013.01); H01L 21/31155 (2013.01); H10D 30/60 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); B82Y 40/00 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a nanowire stack disposed above a substrate, the nanowire stack including a first nanowire and a second nanowire that are vertically stacked;
a gate structure wrapped around each of the first and second nanowires to define a channel region, the gate structure including a first gate sidewall and a second gate sidewall;
a first source/drain region and a second source/drain region arranged on opposite sides of the channel region; and
a first internal spacer arranged on at least a portion of the first gate sidewall between the first nanowire and the second nanowire;
a second internal spacer arranged on at least a portion of the first gate sidewall between the first nanowire and the substrate;
a first external sidewall spacer arranged above the first internal spacer and the second internal spacer, in contact with a first gate dielectric portion of the gate structure, the first gate dielectric portion being between the first external sidewall spacer and a gate electrode portion of the gate structure; and
a second external sidewall spacer arranged above the first internal spacer and the second internal spacer, in contact with a second gate dielectric portion of the gate structure, the second gate dielectric portion being between the second external sidewall spacer and the gate electrode portion of the gate structure.