US 12,363,959 B2
Semiconductor device and method
Chih-Chuan Yang, Tainan (TW); and Shih-Hao Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 12, 2022, as Appl. No. 17/811,988.
Application 17/811,988 is a division of application No. 16/802,873, filed on Feb. 27, 2020, granted, now 11,495,682.
Prior Publication US 2022/0352371 A1, Nov. 3, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 62/82 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 30/794 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H10D 30/0217 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/371 (2025.01); H10D 62/82 (2025.01); H10D 62/822 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0184 (2025.01); H10D 84/0191 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate having a first region and a second region;
a first semiconductor layer directly on the semiconductor substrate in the first region, wherein a first surface of the first semiconductor layer faces a first surface of the semiconductor substrate;
a gate stack in the first region and the second region, the gate stack comprising a gate electrode and a gate dielectric, the gate stack is over the first semiconductor layer in the first region, wherein the gate dielectric is on sidewalls of the first semiconductor layer;
a first epitaxial source/drain region adjacent the gate stack in the first region;
a second epitaxial source/drain region adjacent the gate stack in the second region;
a first high-k dielectric extending continuously under the gate stack in the first region extending between the first semiconductor layer and the first epitaxial source/drain region, wherein the first high-k dielectric completely separates the first semiconductor layer from the first epitaxial source/drain region in a cross-sectional view, wherein a top surface of the first high-k dielectric contacts a bottom surface of the first epitaxial source/drain region, wherein the gate dielectric and the first high-k dielectric comprise the same material; and
a second high-k dielectric extending continuously under the gate stack in the second region, wherein the second high-k dielectric completely separates the second epitaxial source/drain region from the semiconductor substrate in the cross-sectional view.