US 12,363,921 B2
Method for fabricating inductor module
Purakh Raj Verma, Singapore (SG); Su Xing, Singapore (SG); Shyam Parthasarathy, Singapore (SG); and Xiao Yuan Zhi, Singapore (SG)
Assigned to UNITED MICROELECTRONICS CORPORATION, Hsinchu (TW)
Filed by UNITED MICROELECTRONICS CORPORATION, Hsinchu (TW)
Filed on Apr. 28, 2023, as Appl. No. 18/140,635.
Application 18/140,635 is a division of application No. 17/105,524, filed on Nov. 26, 2020, granted, now 11,676,992.
Claims priority of application No. 202010908104.8 (CN), filed on Sep. 2, 2020.
Prior Publication US 2023/0268375 A1, Aug. 24, 2023
Int. Cl. H10D 1/20 (2025.01); H01L 21/768 (2006.01)
CPC H10D 1/20 (2025.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76897 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A method for fabricating an inductor module, comprising steps of:
providing a substrate;
forming a semiconductor component on the substrate;
forming a first inter-level dielectric layer on the substrate to cover the semiconductor component;
forming a first interconnect metal layer and an etching stop layer in the first inter-level dielectric layer, wherein the etching stop layer is formed together with the first interconnect metal layer, and the etching stop layer and the first interconnect metal layer are spaced with each other, wherein the first interconnect metal layer is electrically connected to the semiconductor component;
forming a plurality of second inter-level dielectric layers on the first inter-level dielectric layer, wherein the first inter-level dielectric layer is a single-layer structure and the most bottom second inter-level dielectric layer of the plurality of second inter-level dielectric layers directly covers and contacts the first inter-level dielectric layer, the etching stop layer and the first interconnect metal layer;
etching at least two of the second inter-level dielectric layers by a plasma etching to form a trench penetrating at least two of the second inter-level dielectric layers, wherein the etching stop layer is disposed under the bottom of the trench;
etching the most top second inter-level dielectric layer of the plurality of second inter-level dielectric layers to form a recess penetrating the most top second inter-level dielectric layer, wherein the location of the recess and the location of the trench are spaced with each other;
forming a first metal layer in the trench, wherein the first metal layer is connected with the etching stop layer; and
forming a second metal layer in the recess, wherein the second metal layer is electrically connected to the first interconnect metal layer.