| CPC H10B 63/84 (2023.02) [H10N 70/023 (2023.02); H10N 70/026 (2023.02); H10N 70/8265 (2023.02); H10N 70/881 (2023.02)] | 20 Claims |

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1. A memory device, comprising:
a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each tier individually comprising a conductive structure and an insulative structure;
a barrier material separating opposing portions of a conductive material of the conductive structures;
strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure; and
conductive rails laterally adjacent to the conductive structures of the stack structure, individual conductive rails in horizontal alignment with the barrier material and the conductive material of a respective conductive structure.
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