US 12,363,911 B2
Semiconductor structure and method for forming thereof
Yu-Wei Jiang, Hsinchu (TW); Sheng-Chih Lai, Hsinchu County (TW); Feng-Cheng Yang, Zhudong Township (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 18, 2023, as Appl. No. 18/353,972.
Application 18/353,972 is a division of application No. 17/345,499, filed on Jun. 11, 2021, granted, now 11,785,779.
Claims priority of provisional application 63/167,788, filed on Mar. 30, 2021.
Prior Publication US 2023/0363175 A1, Nov. 9, 2023
Int. Cl. H10B 51/30 (2023.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01)
CPC H10B 51/30 (2023.02) [H10B 51/10 (2023.02); H10B 51/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a stacked structure on the substrate and comprising multiple alternately stacked insulator layers and gate members, wherein the gate members comprise a first gate member, and wherein the insulator layers comprise a first insulator layer underlying the first gate member and a second insulator layer overlying the first gate member;
a core structure in the stacked structure and comprising:
a memory layer;
a channel member on the memory layer; and
a contact member on the channel member; and
a liner member surrounding a portion of the core structure and overlying the first gate member,
wherein conductive material of the first gate member extends continuously from the first insulator layer to the second insulator layer and to the liner member.