US 12,363,910 B2
Three-dimensional memory devices and methods of manufacturing thereof
Meng-Han Lin, Hsinchu (TW); and Chia-En Huang, Xinfeng (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,894.
Application 18/446,894 is a division of application No. 17/458,677, filed on Aug. 27, 2021, granted, now 11,980,035.
Claims priority of provisional application 63/156,771, filed on Mar. 4, 2021.
Prior Publication US 2023/0389327 A1, Nov. 30, 2023
Int. Cl. H10B 51/20 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H10B 51/10 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating memory devices, comprising:
forming a closed-end memory layer extending through a stack of a plurality of insulating layers and a plurality of sacrificial layers, the insulating layers and the sacrificial layers alternatively arranged on top of one another;
forming a closed-end semiconductor layer extending through the stack, the semiconductor layer in contact with the memory layer;
separating the memory layer into a first portion and a second portion;
separating the semiconductor layer into a first portion and a second portion; and
forming a first interconnect structure, second interconnect structure, third interconnect structure, and fourth interconnect structure, each of the first through fourth interconnect structures extending through the stack.