US 12,363,909 B2
Semiconductor memory devices and methods of manufacturing thereof
Peng-Chun Liou, Hsinchu (TW); Ya-Yun Cheng, Taichung (TW); Yi-Ching Liu, Hsinchu (TW); Meng-Han Lin, Hsinchu (TW); and Chia-En Huang, Xinfeng (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/446,043.
Application 18/446,043 is a division of application No. 17/458,237, filed on Aug. 26, 2021, granted, now 11,856,783.
Claims priority of provisional application 63/156,769, filed on Mar. 4, 2021.
Prior Publication US 2023/0403859 A1, Dec. 14, 2023
Int. Cl. H10B 51/20 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H10B 51/10 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating memory devices, comprising:
providing a substrate;
forming a stack comprising alternating insulating layers and sacrificial layers arranged along a vertical direction;
forming a trench extending through the stack and along a lateral direction;
replacing the sacrificial layers with first conductive structures, wherein the first conductive structures extend along the lateral direction;
forming a memory film extending along a sidewall of each first conductive structure;
forming a semiconductor channel along a sidewall of the memory film; and
forming a second conductive structure and a third conductive structure extending along the vertical direction, wherein the second conductive structure and the third conductive structure are in contact with end portions of a sidewall of the semiconductor channel, and wherein widths of the first conductive structures along the lateral direction vary along the vertical direction.