US 12,363,907 B2
Memory device comprising conductive pillars
Yu-Wei Jiang, Hsinchu (TW); Sheng-Chih Lai, Hsinchu County (TW); Tsuching Yang, Taipei (TW); Hung-Chang Sun, Kaohsiung (TW); and Kuo-Chang Chiang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 27, 2023, as Appl. No. 18/341,764.
Application 18/341,764 is a continuation of application No. 17/159,179, filed on Jan. 27, 2021, granted, now 11,729,988.
Claims priority of provisional application 63/040,538, filed on Jun. 18, 2020.
Prior Publication US 2023/0345731 A1, Oct. 26, 2023
Int. Cl. H10B 51/20 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01); H10D 62/80 (2025.01)
CPC H10B 51/20 (2023.02) [H10B 51/10 (2023.02); H10B 51/30 (2023.02); H10D 62/80 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a multi-layer stack, comprising a plurality of conductive layers and a plurality of dielectric layers stacked alternately along a first direction;
a channel layer;
a memory material layer, disposed between the channel layer and each of the conductive layers and the dielectric layers; and
at least three conductive pillars extending in the first direction, wherein the at least three conductive pillars are aligned along a second direction substantially perpendicular to the first direction.