US 12,363,906 B2
3D lateral patterning via selective deposition for ferroelectric devices
Song-Fu Liao, Taipei (TW); Kuo-Chang Chiang, Hsinchu (TW); Hai-Ching Chen, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 19, 2022, as Appl. No. 17/867,983.
Prior Publication US 2024/0032300 A1, Jan. 25, 2024
Int. Cl. H01L 51/10 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/68 (2025.01)
CPC H10B 51/20 (2023.02) [H10B 51/10 (2023.02); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10D 64/689 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a 3D memory device, the method comprising:
forming a plurality of gate lines extending in a lateral direction, wherein the plurality of gate lines are vertically spaced apart from one another by a plurality of dielectric layers extending in the lateral direction;
forming a self-assembled monolayer (SAM) on outer surfaces of the plurality of dielectric layers;
forming a ferroelectric film on outer surfaces of the plurality of gate lines that are vertically separated from the SAM;
forming a semiconductor film on sidewalls of the ferroelectric film that are vertically separated from the SAM; and
forming source/drain lines along the plurality of gate lines extending in a vertical direction perpendicular to the lateral direction.