US 12,363,905 B2
Memory device containing composition-controlled ferroelectric memory elements and method of making the same
Kartik Sondhi, Milpitas, CA (US); Rahul Sharangpani, Fremont, CA (US); Raghuveer S. Makala, Campbell, CA (US); Tiffany Santos, Palo Alto, CA (US); Fei Zhou, San Jose, CA (US); Joyeeta Nag, San Jose, CA (US); Bhagwati Prasad, San Jose, CA (US); and Adarsh Rajashekhar, Santa Clara, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Aug. 19, 2022, as Appl. No. 17/820,997.
Prior Publication US 2024/0064991 A1, Feb. 22, 2024
Int. Cl. H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H10B 51/30 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising:
a vertical semiconductor channel;
a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers and comprising a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material; and
a vertical stack of discrete dielectric material portions comprising the first dielectric metal oxide material and vertically interlaced with the vertical stack of discrete ferroelectric material portions;
wherein:
each discrete dielectric material portion has a first lateral thickness between a respective inner sidewall and a respective outer sidewall;
each of the discrete ferroelectric material portions has a second lateral thickness between a respective inner sidewall and the respective outer sidewall; and
the second lateral thickness is greater than the first lateral thickness.