US 12,363,904 B2
Three-dimensional semiconductor memory device and electronic system including the same
Giyong Chung, Seoul (KR); Jae-Bok Baek, Osan-si (KR); Jaeryong Sim, Suwon-si (KR); and Jeehoon Han, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 3, 2021, as Appl. No. 17/541,444.
Claims priority of application No. 10-2021-0046501 (KR), filed on Apr. 9, 2021.
Prior Publication US 2022/0328511 A1, Oct. 13, 2022
Int. Cl. H10B 43/40 (2023.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/40 (2023.02) [H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
16. A three-dimensional semiconductor memory device, comprising:
a first substrate including a cell array region, a contact region, and a peripheral region;
a peripheral circuit structure with peripheral transistors on the first substrate;
a second substrate on the peripheral circuit structure and extended from the cell array region to the contact region;
a lower insulating layer on the peripheral region, the lower insulating layer being in contact with a side surface of the second substrate;
a stack on the second substrate, the stack including repeatedly alternating first interlayer dielectric layers and gate electrodes;
a source structure extending in a horizontal direction between the second substrate and the stack;
a mold structure on the lower insulating layer, the mold structure including repeatedly alternating sacrificial layers and second interlayer dielectric layers, and the mold structure having a concave top surface on the peripheral region;
a planarization insulating layer covering the stack and the mold structure, the concave top surface of the mold structure being at a level lower than a topmost surface of the stack and a top surface of the planarization insulating layer;
vertical channel structures on the cell array region and the contact region, the vertical channel structures penetrating the planarization insulating layer, the stack, and the source structure and are in contact with the second substrate;
cell contact plugs on the contact region, the cell contact plugs penetrating the planarization insulating layer and are in contact with respective ones of the gate electrodes of the stack; and
through vias on the peripheral region, the through vias penetrating the planarization insulating layer, the mold structure, and the lower insulating layer and are electrically connected to the peripheral transistors of the peripheral circuit structure.