US 12,363,903 B2
Semiconductor memory device and method of manufacturing the same
Dae Hwan Yun, Icheon-si Gyeonggi-do (KR); and Gil Bok Choi, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Oct. 16, 2023, as Appl. No. 18/487,553.
Application 18/487,553 is a division of application No. 17/211,460, filed on Mar. 24, 2021, granted, now 11,812,613.
Claims priority of application No. 10-2020-0125019 (KR), filed on Sep. 25, 2020.
Prior Publication US 2024/0049469 A1, Feb. 8, 2024
Int. Cl. H10B 43/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate;
forming a plurality of holes that pass through the stack in a vertical direction;
sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on sidewalls of each of the plurality of holes;
forming a core insulating layer on a sidewall of the channel layer to fill center regions of the plurality of holes; and
injecting a dopant into a partial region of the core insulating layer so that a dielectric constant of the partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer, the partial region corresponding to a source select transistor or a drain select transistor.