| CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a first semiconductor structure comprising a first substrate, circuit devices on the first substrate, and lower interconnection lines; and
a second semiconductor structure on the first semiconductor structure,
wherein the second semiconductor structure comprises:
a second substrate comprising a first region and a second region;
gate electrodes and interlayer insulating layers alternately stacked in a first direction perpendicular to an upper surface of the second substrate, the gate electrodes extending by different lengths in a second direction on the second region to provide pad regions comprising upper surfaces that are exposed by the interlayer insulating layers;
channel structures penetrating the gate electrodes, extending in the first direction, and each comprising a channel layer, on the first region;
respective contact plugs electrically connected to the pad regions of the gate electrodes, penetrating the gate electrodes, and extending in the first direction; and
contact insulating layers surrounding the respective contact plugs,
wherein the pad regions comprise first and second pad portions, the first pad portions protruding further toward the respective contact plugs than ones of the gate electrodes therebelow to overlap the respective contact plugs in the first direction, and
wherein the gate electrodes have a first thickness on the first region, and the second pad portions have a second thickness greater than the first thickness.
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