US 12,363,886 B2
Semiconductor device structure having a channel layer with different roughness
Szu-Yao Chang, New Taipei (TW); and Chung-Lin Huang, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Mar. 4, 2022, as Appl. No. 17/686,858.
Prior Publication US 2023/0284435 A1, Sep. 7, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/312 (2023.02) 9 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a first word line extending along a first direction;
a second word line physically separated from the first word line and extending along the first direction;
a gate dielectric structure disposed between the first word line and the second word line, wherein the gate dielectric structure has a first part disposed on a sidewall of the first word line and a second part disposed on a sidewall of the second word line, wherein the first part is physically separated from the second part;
a channel layer sandwiched between the first part and the second part of the gate dielectric structure, wherein the channel layer has an exposed portion exposed from and is free from contacting with the gate dielectric structure between the first part and the second part;
a bit line disposed on the channel layer and extending along a second direction substantially perpendicular to the first direction; and
a substrate, wherein the first word line and the second word line define a recess tapered from the bit line toward the substrate, and the gate dielectric structure is disposed within the recess.