US 12,363,464 B2
Optical link system and method for computation
Patrick Gallagher, Santa Clara, CA (US); Thomas W. Baehr-Jones, Santa Clara, CA (US); Michael Gao, Santa Clara, CA (US); and Mitchell A. Nahmias, Santa Clara, CA (US)
Assigned to Luminous Computing, Inc., Santa Clara, CA (US)
Filed by Luminous Computing, Inc., Santa Clara, CA (US)
Filed on Mar. 18, 2024, as Appl. No. 18/608,302.
Application 18/608,302 is a continuation of application No. 17/953,590, filed on Sep. 27, 2022, granted, now 11,937,030.
Application 17/953,590 is a continuation of application No. 17/337,289, filed on Jun. 2, 2021, granted, now 11,490,177, issued on Nov. 1, 2022.
Claims priority of provisional application 63/187,812, filed on May 12, 2021.
Claims priority of provisional application 63/035,667, filed on Jun. 5, 2020.
Prior Publication US 2024/0223923 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04Q 11/00 (2006.01); H04B 10/25 (2013.01)
CPC H04Q 11/0005 (2013.01) [H04B 10/25 (2013.01)] 16 Claims
OG exemplary drawing
 
16. An optical link system, comprising:
a photonics substrate;
a plurality of optical links, each optical link of the plurality of optical links comprising:
one of a plurality of optical waveguides defined on the photonics substrate; and
one of a plurality of first optoelectronic transducers optically coupled to the optical waveguide; and/or one of a plurality of second optoelectronic transducers optically coupled to the optical waveguide; and
a plurality of electronics modules, comprising:
a plurality of first processor electronic modules, each first processor electronic module comprising:
a respective first electronics chip or chiplet mounted on the photonics substrate; and
a respective first processor core defined on the respective first electronics chip or chiplet;
a first switch configured for routing flows of data between each one of the plurality of first processor electronic modules and others of the plurality of electronics modules;
wherein the plurality of optical links communicatively couple the plurality of first processor electronic modules to the first switch;
wherein:
the plurality of first electronic processor modules defines a rectangular array comprising a plurality of rows and a plurality of columns;
each row of the plurality of rows comprises a respective subset of at least three of the first processor electronic modules of the plurality of first processor electronic modules, wherein, for each row, each first processor electronic module of the row is communicatively connected directly to every other nearest neighboring first processor electronic module of the row via a respective optical link of the plurality of optical links; and
each column of the plurality of columns comprises a respective subset of at least three of the first processor electronic modules of the plurality of first processor electronic modules, wherein, for each column, each first processor electronic module of the column is communicatively connected directly to every other nearest neighboring first processor electronic module of the column via a respective optical link of the plurality of optical links.