US 12,363,460 B2
Solid-state imaging sensor
Motonori Ishii, Osaka (JP); and Mitsuyoshi Mori, Kyoto (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., Osaka (JP)
Filed by Panasonic Intellectual Property Management Co., Ltd., Osaka (JP)
Filed on Aug. 11, 2023, as Appl. No. 18/448,673.
Application 18/448,673 is a continuation of application No. PCT/JP2022/012995, filed on Mar. 22, 2022.
Claims priority of application No. 2021-055138 (JP), filed on Mar. 29, 2021.
Prior Publication US 2023/0388676 A1, Nov. 30, 2023
Int. Cl. H04N 25/771 (2023.01); H04N 25/587 (2023.01)
CPC H04N 25/771 (2023.01) [H04N 25/587 (2023.01)] 6 Claims
OG exemplary drawing
 
1. A solid state image sensor comprising at least:
a plurality of pixel cells arranged in a matrix; and
a row control circuit configured to control operations of the plurality of pixel cells,
each of the pixel cells including at least:
an avalanche photodiode configured to convert received light into charge;
a floating diffusion portion configured to store the charge generated in the avalanche photodiode;
a transfer transistor connected to the avalanche photodiode and the floating diffusion portion;
a reset transistor connected to a first power supply and the floating diffusion portion;
an amplifier transistor connected to a second power supply and the floating diffusion portion to output a voltage signal responsive to an amount of charge stored in the floating diffusion portion;
a selection transistor connected to the amplifier transistor to transfer an output signal from the amplifier transistor to a vertical signal line;
a count transistor connected to the floating diffusion portion; and
a capacitor having terminals one of which is connected to the count transistor,
the row control circuit being configured to be capable of applying three different levels of first to third voltages to gates of the reset transistors,
the first voltage being set to be higher than the second voltage and the second voltage being set to be higher than the third voltage,
applying the first voltage to gates of the reset transistors by the row control circuit fixing electric potentials of the floating diffusion portions at a same level as a power supply voltage of the first power supply,
applying the second voltage to the gates of the reset transistors by the row control circuit changing potentials directly below the gates of the reset transistors to levels between potentials of sources of the reset transistors and potentials of drains of the reset transistors, and
applying the third voltage to the gates of the reset transistors by the row control circuit turning the reset transistors off.