| CPC H04L 67/63 (2022.05) [H04L 41/5019 (2013.01); H04L 45/02 (2013.01)] | 28 Claims |

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1. A node comprising:
a memory including instructions; and
processing circuitry that, when in operation, is configured by the instructions to:
receive a storage interest packet, the storage interest packet including an indication differentiating the storage interest packet from other ICN interests;
forward the storage interest packet;
receive a storage data packet in response to the storage interest packet, the storage data packet including an indication that the storage data packet is not to be cached, the storage data packet including node information for a node that created the storage data packet, wherein the storage interest packet includes a set of selectors, wherein the set of selectors is used by nodes to determine storage requirements for data indicated in the storage interest packet, and wherein the node that created the storage data packet met the storage requirements; and
transmit the storage data packet in accordance with a pending interest table (PIT) entry corresponding to the storage interest packet.
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