US 12,363,018 B2
Circuit and method for timestamp jitter reduction
Eliya Babitsky, Caesarea (IL); Moran Noiman, Kiryat Ono (IL); Adi Katz, Ramat Gan (IL); Yaakov Yehezkel, Rehovot (IL); Ofer Halili, Karkur (IL); and Tal Robinson, Giv'at Shmuel (IL)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Jul. 28, 2022, as Appl. No. 17/815,635.
Prior Publication US 2024/0048469 A1, Feb. 8, 2024
Int. Cl. H04L 43/106 (2022.01); H04L 43/087 (2022.01)
CPC H04L 43/106 (2013.01) [H04L 43/087 (2013.01)] 45 Claims
OG exemplary drawing
 
1. A circuit comprising:
recursive filter logic, the circuit configured to:
(i) generate a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic, the recursive filter logic configured to reduce jitter in the filtered timestamp relative to jitter of the received timestamp, the jitter of the received timestamp representing a deviation of the received timestamp from a target timestamp, and
(ii) output the filtered timestamp generated.