US 12,362,769 B2
Apparatus and method for processing transmit data in a transmit data path including parallel FEC encoding
Sailaja Akkem, Austin, TX (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Oct. 5, 2023, as Appl. No. 18/481,340.
Claims priority of provisional application 63/378,687, filed on Oct. 7, 2022.
Prior Publication US 2024/0120948 A1, Apr. 11, 2024
Int. Cl. H03M 13/29 (2006.01); H03M 13/00 (2006.01)
CPC H03M 13/2903 (2013.01) [H03M 13/6561 (2013.01)] 27 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a data width converter in a transmit data path, the data width converter including an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width;
a forward error correction (FEC) encoder in parallel with the transmit data path, the FEC encoder including an input to receive the second output data stream at the second output bit width, the FEC encoder including an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width, the parity bits for insertion in the first output data stream having the first output bit width; and
a latency predictor, the latency predictor operably coupled to the data width converter, the latency predictor comprising a look up table of latency values respectively associated with clock count values.