US 12,362,712 B2
Class AB monticelli output stage design with bias temperature instability tolerance
Vivek Varier, Tucson, AZ (US); Srinivas Kumar Pulijala, Tucson, AZ (US); Vadim Valerievich Ivanov, Tucson, AZ (US); and Jerry L. Doorenbos, Tucson, AZ (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 31, 2022, as Appl. No. 17/589,585.
Prior Publication US 2023/0246605 A1, Aug. 3, 2023
Int. Cl. H03F 3/30 (2006.01); H03F 3/21 (2006.01)
CPC H03F 3/21 (2013.01) [H03F 3/3022 (2013.01); H03F 2203/21127 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a p-channel transistor having a gate, a source, and a drain;
an n-channel transistor having a drain coupled to the drain of the p-channel transistor at an output of the circuit, the n-channel transistor having a gate and a source;
a first transistor having first and second terminals and a control terminal, the control terminal coupled to the gate of the p-channel transistor, the first terminal coupled to the source of the p-channel transistor;
first current mirror circuitry coupled to the second terminal of the first transistor;
second current mirror circuitry coupled to the first current mirror circuitry, the second current mirror circuitry having a terminal;
a second transistor having first and second terminals and a control terminal, the first terminal of the second transistor coupled to the gate of the p-channel transistor, the second terminal of the second transistor coupled to the gate of the n-channel transistor, the control terminal of the second transistor coupled to the terminal of the second current mirror circuitry; and
a current source having a first terminal coupled to the terminal of the second current mirror circuitry and to the control terminal of the second transistor, the current source having a second terminal coupled to the source of the n-channel transistor.