US 12,362,705 B2
Oscillator regulation
Harald Garvik, Trondheim (NO); and Erlend Strandvik, Trondheim (NO)
Assigned to Nordic Semiconductor ASA, Trondheim (NO)
Appl. No. 18/290,273
Filed by Nordic Semiconductor ASA, Trondheim (NO)
PCT Filed May 11, 2022, PCT No. PCT/EP2022/062746
§ 371(c)(1), (2) Date Nov. 10, 2023,
PCT Pub. No. WO2022/238463, PCT Pub. Date Nov. 17, 2022.
Claims priority of application No. 2106734 (GB), filed on May 12, 2021.
Prior Publication US 2024/0267000 A1, Aug. 8, 2024
Int. Cl. H03B 5/32 (2006.01); H03B 5/36 (2006.01); H03L 5/00 (2006.01)
CPC H03B 5/32 (2013.01) [H03L 5/00 (2013.01); H03B 5/36 (2013.01); H03B 2200/0012 (2013.01); H03B 2200/0066 (2013.01); H03B 2201/031 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method, the method comprising regulating an amplitude of an oscillator using an amplitude regulation algorithm, the amplitude regulation algorithm comprising:
a) acquiring a digital representation encoding a bias current;
b) monitoring an oscillation amplitude of the oscillator at a node using one or more peak detectors;
c) using the peak detector(s) to carry out a comparison of the oscillation amplitude at the node with an upper amplitude threshold and a lower amplitude threshold,
d) if the comparison determines that said oscillation amplitude is greater than said upper amplitude threshold, updating said digital representation to encode a reduced bias current and storing said updated digital representation;
e) if the comparison determines that said oscillation amplitude is lower than said lower amplitude threshold updating said digital representation to encode an increased bias current and storing said updated digital representation;
f) entering a sleep state wherein the peak detector(s) is/are disabled before repeating steps b) to e) using said updated digital representation as said digital representation; and
g) intermittently enabling the peak detector(s) between sleep states and running steps b) to e) of the amplitude regulation algorithm.