| CPC H01Q 21/00 (2013.01) [H01Q 9/04 (2013.01); H01Q 21/06 (2013.01); H01Q 21/24 (2013.01)] | 24 Claims |

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1. An integrated dilation and feed circuit comprising:
an asymmetric a dilation layer comprising a pair of dilation circuit signal paths;
an asymmetric reactive combiner layer comprising a pair of reactive combiner circuits, said asymmetric reactive combiner circuit layer disposed over said asymmetric dilation layer such that said pair of reactive combiner circuits are coupled to respective ones of said pair of dilation circuit signal paths;
a symmetric feed layer having a plurality of feed circuits symmetrically disposed thereon, said symmetric feed layer disposed over said asymmetric asymmetric reactive combiner layer such that each of said symmetrically disposed plurality of feed circuits are coupled to one of said pair of asymmetric, reactive combiner circuits, wherein said symmetric feed layers is both physically and electrically symmetric; and
a symmetric slot layer having a like plurality of slots symmetrically disposed thereon, said symmetric slot layer disposed over said symmetric feed layer such that each of said plurality of feed circuits intersect a respective one of said plurality of slots, wherein said symmetric slot layer is both physically and electrically symmetric.
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