| CPC H01L 24/48 (2013.01) [H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/48227 (2013.01)] | 20 Claims |
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1. A semiconductor package comprising:
a package substrate;
a chip stack structure on an upper surface of the package substrate, the chip stack structure including at least two semiconductor chips; and
an external connection terminal on a lower surface of the package substrate,
wherein the at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip is an uppermost one from among the at least two semiconductor chips and is connected to a first bonding pad of the package substrate through a first wire,
the second semiconductor chip is under the first semiconductor chip from among the at least two semiconductor chips and is connected to a second bonding pad of the package substrate through a second wire,
the first bonding pad is connected to the second bonding pad through an upper wiring line on the package substrate,
the upper wiring line horizontally extends on the package substrate and includes a first portion and a second portion, the first portion extending from the first bonding pad in a direction away from the at least two semiconductor chips, the second portion horizontally extending between the first bonding pad and the second bonding pad,
the first bonding pad is farther from the external connection terminal than the second bonding pad,
the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate and is connected to the second bonding pad through the wiring line, the first bonding pad, and the upper wiring line,
the first wire, the first bonding pad, the first portion of the upper wiring line, and the wiring line are sequentially connected, and
a length of the second portion of the upper wiring line is proportional to a difference between a length of the first wire and a length of the second wire.
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