US 12,362,282 B2
Semiconductor structure and manufacturing method thereof
Ching-Jung Yang, Taoyuan (TW); Hsien-Wei Chen, Hsinchu (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 23, 2022, as Appl. No. 17/750,423.
Application 17/076,811 is a division of application No. 16/413,605, filed on May 16, 2019, granted, now 10,840,190, issued on Nov. 17, 2020.
Application 17/750,423 is a continuation of application No. 17/076,811, filed on Oct. 22, 2020, granted, now 11,373,953.
Prior Publication US 2022/0285279 A1, Sep. 8, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5384 (2013.01) [H01L 21/76802 (2013.01); H01L 23/481 (2013.01); H01L 23/522 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/09 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 21/76807 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a lower portion including a first conductive pad, a first conductive connector passing through the first conductive pad, a first dielectric layer covering the first conductive pad and laterally isolating the first conductive connector from the first conductive pad, a first dummy connector embedded in the first dielectric layer, and a first interconnect structure below the first dielectric layer, wherein the first conductive pad is directly in contact with the first interconnect structure, and wherein a bottom surface of the first conductive pad and a bottom surface of the first conductive connector are aligned with a top surface of the first interconnect structure;
an upper portion disposed above the lower portion, the upper portion including a second semiconductor substrate, a second conductive connector underlying the second semiconductor substrate and bonded to the first conductive connector, a second dielectric layer bonded to the first dielectric layer, a dummy pad and a second dummy connector laterally covered by the second dielectric layer, and a second interconnect structure interposed between the second dielectric layer and the second semiconductor substrate, wherein the second dummy connector has one end bonded to the first dummy connector and an opposing end landing on the dummy pad;
a through substrate via penetrating through the second semiconductor substrate, and a bottom surface of the through substrate via is lower than a bottom surface of the second semiconductor substrate; and
a redistribution structure disposed on the second semiconductor substrate and the through substrate via, wherein the through substrate via extends into the second interconnect structure to be electrically coupled to the lower portion through the upper portion, and the through substrate via and the first conductive connector are tapered toward a same direction.