US 12,362,281 B2
Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof
Tsung-Ling Tsai, Hsinchu (TW); Shen-Nan Lee, Hsinchu County (TW); Mrunal A. Khaderbad, Hsinchu (TW); Chung-Wei Hsu, Hsinchu (TW); Chen-Hao Wu, Hsinchu (TW); and Teng-Chun Tsai, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/357,500.
Application 17/313,558 is a division of application No. 16/399,697, filed on Apr. 30, 2019, granted, now 11,004,794, issued on May 11, 2021.
Application 18/357,500 is a continuation of application No. 17/313,558, filed on May 6, 2021, granted, now 11,776,910.
Claims priority of provisional application 62/690,586, filed on Jun. 27, 2018.
Prior Publication US 2023/0361042 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/7684 (2013.01); H01L 21/76847 (2013.01); H01L 21/76879 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53209 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An interconnect structure comprising:
a dielectric layer; and
a via disposed in the dielectric layer, wherein the via connects a first interconnect and a second interconnect, and further wherein the via includes:
a barrier-free via plug and a metal liner, wherein the barrier-free via plug is disposed on the first interconnect, the metal liner is disposed on and abuts a top surface of the barrier-free via plug, and the metal liner is disposed between the barrier-free via plug and the second interconnect,
wherein a first sidewall of the via is formed by a first sidewall portion of the metal liner and a first sidewall of the barrier-free via plug and a second sidewall of the via is formed by a second sidewall portion of the metal liner and a second sidewall of the barrier-free via plug, and
the first sidewall portion of the metal liner, the first sidewall of the barrier-free via plug, the second sidewall of the metal liner, and the second sidewall of the barrier-free via plug abut the dielectric layer.