US 12,362,280 B2
Semiconductor device and method of manufacturing the same
Takeshi Kawamura, Tokyo (JP)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Oct. 28, 2022, as Appl. No. 17/976,598.
Application 14/683,788 is a division of application No. 13/704,113, granted, now 9,030,014, issued on May 12, 2015, previously published as PCT/JP2010/060050, filed on Jun. 14, 2010.
Application 17/976,598 is a continuation of application No. 17/061,141, filed on Oct. 1, 2020, granted, now 11,515,257.
Application 17/061,141 is a continuation of application No. 16/526,018, filed on Jul. 30, 2019, abandoned.
Application 16/526,018 is a continuation of application No. 16/033,962, filed on Jul. 12, 2018, granted, now 10,418,328, issued on Sep. 17, 2019.
Application 16/033,962 is a continuation of application No. 15/092,151, filed on Apr. 6, 2016, granted, now 10,049,984, issued on Aug. 14, 2018.
Application 15/092,151 is a continuation of application No. 14/683,788, filed on Apr. 10, 2015, granted, now 9,337,016, issued on May 10, 2016.
Prior Publication US 2023/0056809 A1, Feb. 23, 2023
Int. Cl. H10D 30/60 (2025.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H10D 30/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H01L 23/485 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/02126 (2013.01); H01L 21/022 (2013.01); H01L 21/28518 (2013.01); H01L 21/28568 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76805 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76852 (2013.01); H01L 21/76889 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 22/26 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H10D 30/021 (2025.01); H10D 30/601 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H01L 21/76885 (2013.01); H01L 23/485 (2013.01); H01L 2924/0002 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate;
a first insulating film formed over a main surface of the semiconductor substrate;
a second insulating film formed over the first insulating film;
a third insulating film formed over the second insulating film;
a first conductor formed in the first insulating film and the second insulating film;
a second conductor formed in the second insulating film and the third insulating film; and
a wiring trench formed in the second insulating film and the third insulating film,
wherein an upper surface of the first conductor is formed higher than a lower surface of the second insulating film which is in contact with the first insulating film,
wherein a lowermost lower surface of the second conductor is formed in the first insulating film,
wherein a dielectric constant of the third insulating film is lower than a dielectric constant of the first insulating film, and
wherein a lowermost lower surface of the wiring trench is formed in the second insulating film, and wherein another lower surface of the wiring trench is formed on the upper surface of the first conductor.