US 12,362,276 B2
Semiconductor package having a semiconductor device bonded to a circuit substrate through a floated or grounded dummy conductor and method of manufacturing the same
Feng-Cheng Hsu, New Taipei (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 9, 2022, as Appl. No. 17/835,991.
Application 17/835,991 is a continuation of application No. 16/871,035, filed on May 10, 2020, granted, now 11,387,183.
Application 16/871,035 is a continuation of application No. 15/398,724, filed on Jan. 5, 2017, granted, now 10,692,813, issued on Jun. 23, 2020.
Claims priority of provisional application 62/427,135, filed on Nov. 28, 2016.
Prior Publication US 2022/0302030 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 21/6835 (2013.01); H01L 23/49811 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14517 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17517 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/94 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a circuit substrate, comprising a plurality of first conductive pads, a plurality of second conductive pads each separated from the plurality of first conductive pads, and a solder mask layer with a plurality of first recesses and a plurality of second recesses defined therein; and
a semiconductor device, disposed on the circuit substrate, wherein the semiconductor device comprises:
an integrated circuit, comprising a plurality of first connecting pads and a plurality of second connecting pads;
a plurality of connecting terminals, disposed over and electrically coupled to the integrated circuit, wherein the plurality of connecting terminals are electrically coupled to the integrated circuit by disposing on the plurality of first connecting pads; and
at least one dummy conductor, disposed over and electrically isolated from the integrated circuit, wherein the at least one dummy conductor is electrically isolated from the integrated circuit by disposing on a respective one of the plurality of second connecting pads, wherein the semiconductor device is bonded to the circuit substrate through connecting the plurality of connecting terminals to the plurality of first conductive pads and connecting the at least one dummy conductor to one of the plurality of second conductive pads, and there is a level difference between horizontal interfaces of the plurality of connecting terminals and the plurality of first conductive pads and a horizontal interface of the at least one dummy conductor and the one of the plurality of second conductive pads,
wherein the at least one dummy conductor is electrically floated or grounded.
 
10. A semiconductor package, comprising:
an integrated circuit, comprising a plurality of first connecting pads and a plurality of second connecting pads;
a plurality of connecting terminals, disposed on and electrically connected to the integrated circuit, wherein the plurality of connecting terminals are electrically coupled to the integrated circuit by disposing on the plurality of first connecting pads;
a plurality of dummy conductors, disposed on and electrically isolated from the integrated circuit, wherein the plurality of dummy conductors are electrically isolated from the integrated circuit by disposing on the plurality of second connecting pads; and
a redistribution layer circuit structure, comprising a plurality of first conductive pads connected to the plurality of connecting terminals, a plurality of second conductive pads connected to the plurality of dummy conductors and separated from the plurality of first conductive pads,
wherein there is a level difference between horizontal interfaces of the plurality of connecting terminals and the redistribution layer circuit structure and horizontal interfaces of the plurality of dummy conductors and the redistribution layer circuit structure, and
wherein the plurality of dummy conductors are electrically floated or grounded.
 
17. A method of manufacturing a semiconductor package, comprising:
providing a circuit structure having a plurality of first conductive pads, a plurality of second conductive pads each separated from the plurality of first conductive pads, and a solder mask layer having a plurality of first recesses and a plurality of second recesses formed therein;
providing a semiconductor device comprising an integrated circuit comprising a plurality of first connecting pads and a plurality of second connecting pads, a plurality of connecting terminals disposed over and electrically coupled to the integrated circuit and at least one dummy conductor disposed over and electrically isolated from the integrated circuit, wherein the plurality of connecting terminals are electrically coupled to the integrated circuit by disposing on the plurality of first connecting pads, and the at least one dummy conductor is electrically isolated from the integrated circuit by disposing on a respective one of the plurality of second connecting pads; and
mounting the semiconductor device to the circuit structure by connecting the plurality of connecting terminals to the plurality of first conductive pads and connecting the at least one dummy conductor to one of the plurality of second conductive pads, wherein there is a level difference between horizontal interfaces of the plurality of connecting terminals and the plurality of first conductive pads and a horizontal interface of the at least one dummy conductor and the one of the plurality of second conductive pads along a stacking direction of the semiconductor device and the circuit structure, and the at least one dummy conductor is electrically floated or grounded.