| CPC H01L 23/5223 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76843 (2013.01); H01L 21/7685 (2013.01); H01L 23/5226 (2013.01); H01L 23/53266 (2013.01); H10D 1/042 (2025.01); H10D 1/716 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
a first conductive feature formed on a semiconductor substrate;
first, second, and third metallization layers configured on the semiconductor substrate above the first conductive feature, wherein the first, second, and third metallization layers each comprises a respective first, second, and third metallization structures formed in first, second, and third dielectric layers, respectively;
first, second, and third via structures formed in fourth, fifth, and sixth dielectric layers, respectively, wherein the first via structure extends from the first conductive feature to the first metallization layer, wherein:
the first metallization structure comprises a first side surface, a second side surface and a first bottom surface, wherein the first side surface, the second side surface and the first bottom surface are in direct contact with a first barrier layer, and
the first via structure comprises a first top surface, a third side surface, a fourth side surface and a second bottom surface, wherein the third side surface, the fourth side surface and the second bottom surface are in direct contact with a second barrier layer, and wherein the first top surface is in direct contact with the first barrier layer;
the second metallization structure comprises a fifth side surface, a sixth side surface, a second top surface, and a third bottom surface, wherein the fifth side surface, the sixth side surface and the third bottom surface are in direct contact with a third barrier layer,
the second via structure comprises a third top surface, a seventh side surface, an eighth side surface, and a fourth bottom surface, wherein the seventh side surface, the eighth side surface and the fourth bottom surface are in direct contact with a fourth barrier layer, and wherein the third top surface is in direct contact with the third barrier layer and the fourth barrier layer is in direct contact with the first metallization structure;
a conductive etch stop structure formed below the third via structure and on at least part of the second metallization structure of the second metallization layer to electrically couple the second metallization structure and the third via structure, wherein the first via structure, the first metallization structure, the conductive etch stop structure, the second via structure, the second metallization structure, and the third via structure electrically couple the third metallization structure to the first conductive feature; and
first and second capacitors formed in a single via hole embedded in a plurality of dielectric layers, wherein the first capacitor comprises a first metal electrode, a second metal electrode, and a first dielectric structure sandwiched between the first and second metal electrodes, and the second capacitor comprises the second metal electrode, a third metal electrode, and a second dielectric structure sandwiched between the second and third metal electrodes, wherein each of the first, second, and third metal electrodes and the first and second dielectric structures extends into at least the first, third and fourth dielectric layers,
wherein the first metal electrode comprises a first continuously straight metal sidewall, a second continuously straight metal sidewall opposite the first continuously straight metal sidewall, a first continuous metal bottom portion that integrally connects the first and second continuously straight metal sidewalls at acute and obtuse angles, respectively, the second metal electrode comprises a third continuously straight metal sidewall, a fourth continuously straight metal sidewall opposite the third continuously straight metal sidewall, a second continuous metal bottom portion that integrally connects the third and fourth continuously straight metal sidewalls at acute and obtuse angles, and the third metal electrode comprises a fifth continuously straight metal sidewall, a sixth continuously straight metal sidewall opposite the fifth continuously straight metal sidewall, a third continuous metal bottom portion that integrally connects the fifth and sixth continuously straight metal sidewalls at acute and obtuse angles,
wherein the first, third, and fifth continuously straight metal sidewalls are parallel to each other and the second, fourth, sixth continuously straight metal sidewalls are parallel to each other,
wherein each of the first, the second, and the third metal electrodes, and the first and second dielectric structure are formed in a single trench tapering towards the first continuous metal bottom portion,
and wherein the first dielectric structure comprises a first continuously straight dielectric sidewall sandwiched between the first and third continuously straight metal sidewalls, a second continuously straight dielectric sidewall sandwiched between the second and fourth continuously straight metal sidewalls, a first continuously dielectric bottom portion that integrally connects the first and second continuously straight dielectric sidewalls at acute and obtuse angles, respectively, and
the second dielectric structure comprises a third continuously straight dielectric sidewall sandwiched between the third and fifth continuously straight metal sidewalls, a fourth continuously straight dielectric sidewall sandwiched between the fourth and sixth continuously straight metal sidewalls, a second continuous dielectric bottom portion that integrally connects the third and fourth continuously straight dielectric sidewalls at acute and obtuse angles, respectively.
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