US 12,362,270 B2
Package structure and method of fabricating the same
Kris Lipu Chuang, Hsinchu (TW); Tzu-Sung Huang, Tainan (TW); Chih-Wei Lin, Hsinchu County (TW); Yu-fu Chen, Hsinchu (TW); Hsin-Yu Pan, Taipei (TW); and Hao-Yi Tsai, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 23, 2022, as Appl. No. 17/679,052.
Prior Publication US 2023/0268260 A1, Aug. 24, 2023
Int. Cl. H01L 23/22 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49838 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/32 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2224/211 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/107 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a first redistribution layer having a core region and a peripheral region surrounding the core region, wherein the first redistribution layer comprises:
a first dielectric layer and a second dielectric layer stacked on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are located in the core region and the peripheral region;
a plurality of first conductive patterns embedded in the first dielectric layer and the second dielectric layer in the core region, wherein the plurality of first conductive patterns is arranged in the core region with a pattern density that gradually increases from a center of the core region to a boundary of the core region, or arranged in the core region with a pattern density that gradually decreases from the center of the core region to the boundary of the core region; and
a plurality of second conductive patterns embedded in the first dielectric layer and the second dielectric layer in the peripheral region;
a semiconductor die disposed on the core region over the plurality of first conductive patterns and overlapped with the plurality of first conductive patterns; and
a plurality of through vias disposed on the peripheral region and electrically connected to the plurality of second conductive patterns.