US 12,362,269 B2
Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods
Michelle Yejin Kim, San Diego, CA (US); Kuiwon Kang, San Diego, CA (US); Joan Rey Villarba Buot, Escondido, CA (US); and Ching-Liou Huang, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Oct. 18, 2021, as Appl. No. 17/451,302.
Prior Publication US 2023/0118028 A1, Apr. 20, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01)] 37 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package, comprising:
a package substrate that extends in a first direction, comprising:
a first metallization layer comprising:
a first insulating layer comprising an outer surface; and
a first metal layer comprising one or more first metal traces embedded in the first insulating layer, wherein the one or more first metal traces each comprise:
an outer metal portion having a first height in a second direction orthogonal to the first direction; and
an inner metal portion disposed inside the outer metal portion, the inner metal portion having a second height in the second direction less than the first height;
a die comprising one or more die interconnects each coupled to the first metallization layer in a vertical area between the die and the outer surface of the first metallization layer; and
a second metal layer laterally adjacent to the vertical area and vertically adjacent to the outer surface of the first insulating layer, the second metal layer comprising one or more second metal interconnects each coupled to a first metal trace among the one or more first metal traces in the first metal layer of the first metallization layer.