US 12,362,264 B2
Semiconductor device
Toru Sugiyama, Musashino (JP); Akira Yoshioka, Yokohama (JP); Hung Hung, Kawasaki (JP); Yasuhiro Isobe, Ota (JP); and Hitoshi Kobayashi, Yamato (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Mar. 2, 2022, as Appl. No. 17/653,201.
Claims priority of application No. 2021-148365 (JP), filed on Sep. 13, 2021.
Prior Publication US 2023/0080613 A1, Mar. 16, 2023
Int. Cl. H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01)
CPC H01L 23/49513 (2013.01) [H01L 23/49575 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 25/072 (2013.01); H10D 30/47 (2025.01); H10D 62/8503 (2025.01); H01L 2224/32245 (2013.01); H01L 2224/48245 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first terminal;
a second terminal;
a first chip comprising:
a substrate electrically connected to the second terminal,
a nitride semiconductor layer located on the substrate,
a first drain electrode located on the nitride semiconductor layer and electrically connected to the first terminal,
a first source electrode located on the nitride semiconductor layer and electrically connected to the second terminal,
a lateral main current path between the first drain electrode and the first source electrode, and
a substrate capacitance formed between the first drain electrode and the substrate without the inclusion of a separate capacitor; and
a resistor connected in series in a path including the substrate capacitance between the first drain electrode and the second terminal, wherein a series resonance between the substrate capacitance and a parasitic inductance of one or more wires connected to the semiconductor device is absorbed by the resistor to suppress ringing of a drain current.