US 12,362,263 B2
Electronic package and method of fabricating the same
Pin-Jing Su, Taichung (TW); and Cheng-Kai Chang, Taichung (TW)
Assigned to SILICONWARE PRECISION INDUSTRIES CO., LTD., Taichung (TW)
Filed by SILICONWARE PRECISION INDUSTRIES CO., LTD., Taichung (TW)
Filed on Apr. 24, 2024, as Appl. No. 18/644,937.
Application 18/644,937 is a division of application No. 16/568,990, filed on Sep. 12, 2019, granted, now 12,002,737.
Claims priority of application No. 108116577 (TW), filed on May 14, 2019.
Prior Publication US 2024/0282674 A1, Aug. 22, 2024
Int. Cl. H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/566 (2013.01); H01L 23/3157 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 24/33 (2013.01); H01L 24/83 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method of fabricating an electronic package, comprising:
providing an encapsulating layer embedded with a plurality of conductive pillars and at least one interposer board having a plurality of through-silicon vias, wherein the plurality of conductive pillars are free from being formed in the at least one interposer board and any interposer board, wherein the plurality of conductive pillars are in direct contact with the encapsulating layer and are free from being in direct contact with the at least one interposer board and the plurality of through-silicon vias, wherein a surface of the encapsulating layer, a surface of the at least one interposer board, end surfaces of the plurality of through-silicon vias and end surfaces of the plurality of conductive pillars are horizontally coplanar; and
disposing at least one semiconductor chip as an electronic component on one side of the encapsulating layer, and electrically connecting the electronic component to the conductive pillars and the through-silicon vias by a plurality of conductive bumps, wherein the plurality of conductive bumps are in direct contact with the electronic component, the plurality of conductive pillars, and the plurality of through-silicon vias, wherein the electronic component is free from being embedded in the encapsulating layer.