US 12,362,261 B2
Semiconductor device and method of manufacture
Chih-Chia Hu, Taipei (TW); Sen-Bor Jan, Tainan (TW); Hsien-Wei Chen, Hsinchu (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 19, 2023, as Appl. No. 18/355,098.
Application 16/725,732 is a division of application No. 16/122,318, filed on Sep. 5, 2018, granted, now 10,515,874, issued on Dec. 24, 2019.
Application 18/355,098 is a continuation of application No. 17/815,515, filed on Jul. 27, 2022, granted, now 11,791,243.
Application 17/815,515 is a continuation of application No. 17/181,784, filed on Feb. 22, 2021, granted, now 11,462,458, issued on Oct. 4, 2022.
Application 17/181,784 is a continuation of application No. 16/725,732, filed on Dec. 23, 2019, granted, now 10,930,580, issued on Feb. 23, 2021.
Claims priority of provisional application 62/592,539, filed on Nov. 30, 2017.
Prior Publication US 2023/0369170 A1, Nov. 16, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76805 (2013.01); H01L 22/32 (2013.01); H01L 23/528 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/09 (2013.01); H01L 24/80 (2013.01); H01L 24/08 (2013.01); H01L 2224/03 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/80447 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor substrate;
an interconnect structure over the semiconductor substrate, the interconnect structure comprising a first conductive feature in a first dielectric layer;
an insulating bonding layer over the first dielectric layer;
a second conductive feature over the first dielectric layer and in the insulating bonding layer;
a first bond pad extending from a top surface of the insulating bonding layer to the first conductive feature; and
a second bond pad extending from a top surface of the insulating bonding layer into the second conductive feature such that the second bond pad is partially embedded in the second conductive feature.