US 12,362,246 B2
Interposer including stepped surfaces and methods of forming the same
Yu-Sheng Lin, Zhubei (TW); Hsin-Hsien Lee, Taoyuan County (TW); Jyun-Lin Wu, Hsinchu (TW); and Yao-Chun Chuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 22, 2022, as Appl. No. 17/871,375.
Prior Publication US 2024/0030076 A1, Jan. 25, 2024
Int. Cl. H01L 23/13 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/13 (2013.01) [H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
an interposer including a vertical stack of a semiconductor substrate embedding through-substrate via structures and dielectric material layers embedding metal interconnect structures, wherein the interposer comprises a first planar surface, a set of non-horizontal surfaces comprising concave surfaces or tapered surfaces and having a top periphery that is adjoined to a periphery of the first planar surface, a frame-shaped surface which has an outer periphery and an inner periphery that is laterally offset inward relative to the outer periphery and is adjoined to a bottom periphery of the set of non-horizontal surfaces, interposer sidewalls adjoined to the frame-shaped surface, and a second planar surface adjoined to the interposer sidewalls, wherein the set of non-horizontal surfaces comprises sidewalls of the dielectric material layers and upper sidewalls of the semiconductor substrate which are laterally offset inward relative to lower sidewalls of the semiconductor substrate by the frame-shaped surface and have a top periphery that coincides with a bottom periphery of the sidewalls of the dielectric material layers;
at least one semiconductor die attached to the interposer through a respective array of solder material portions; and
an underfill material portion located between the interposer and the at least one semiconductor die and contacting a portion of the first planar surface.