US 12,362,241 B2
Semiconductor structure and method for forming a semiconductor structure
Richard Geiger, Munich (DE); Klaus Herold, Munich (DE); Harald Gossner, Riemerling (DE); Martin Ostermayr, Woerth (DE); Georgios Panagopoulos, Munich (DE); Johannes Rauh, Kirchseeon (DE); Joachim Singer, Neubiberg (DE); and Thomas Wagner, Regelsbach (DE)
Assigned to Intel corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 17, 2021, as Appl. No. 17/644,801.
Prior Publication US 2023/0197537 A1, Jun. 22, 2023
Int. Cl. H01L 23/58 (2006.01); H01L 21/66 (2006.01); H01L 23/48 (2006.01); H01L 29/10 (2006.01)
CPC H01L 22/32 (2013.01) [H01L 23/481 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a plurality of transistors located at a front side of a semiconductor substrate;
a test structure located at the front side of the semiconductor substrate;
a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.