US 12,362,239 B2
Self aligned contact scheme
Yu-Lien Huang, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 8, 2024, as Appl. No. 18/629,384.
Application 17/717,730 is a division of application No. 16/746,544, filed on Jan. 17, 2020, granted, now 11,302,577, issued on Apr. 12, 2022.
Application 18/629,384 is a continuation of application No. 17/717,730, filed on Apr. 11, 2022, granted, now 11,978,670.
Prior Publication US 2024/0258168 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/0337 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76834 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a gate structure comprising a gate dielectric, a gate electrode, and a first gate spacer and a second gate spacer disposed on opposing sides of the gate electrode;
a first hard mask layer over the gate electrode and the gate dielectric;
a second hard mask layer disposed over the first gate spacer, the second hard mask layer being a different material than a material of the first hard mask layer, the second hard mask layer and the first hard mask layer contacting the first gate spacer; and
a conductive feature adjacent the first gate spacer.
 
9. A device comprising:
a gate structure, wherein the gate structure comprises a gate electrode over a gate dielectric, and a first gate spacer and a second gate spacer disposed on either side of the gate electrode;
a first source/drain and a second source/drain on opposing sides of the gate structure;
a first etch stop layer on a sidewall of the gate structure;
a first hard mask over the gate electrode; and
a second hard mask over the first etch stop layer.
 
15. A device comprising:
a gate structure over a channel region, the gate structure comprising a gate electrode, a gate mask over the gate electrode, and a first gate spacer and a second gate spacer on opposing sides of the gate electrode, and
a first source/drain and a second source/drain on opposing sides of the gate structure;
a first dielectric layer over a sidewall of the first gate spacer and on an upper surface of the first source/drain, the first gate spacer being between the first dielectric layer and the gate electrode;
a second dielectric layer over a sidewall of the second gate spacer and on an upper surface of the second source/drain, the second gate spacer being between the second dielectric layer and the gate electrode;
a third dielectric layer adjacent the second dielectric layer, the second dielectric layer being between the third dielectric layer and the second gate spacer;
a first hard mask over the first gate spacer and the first dielectric layer; and
a second hard mask over the second gate spacer and the second dielectric layer, wherein the first hard mask and second hard mask have upper surfaces level with an upper surface of the third dielectric layer.