US 12,362,228 B2
Semiconductor package and method
Chen-Hua Yu, Hsinchu (TW); Wei-Yu Chen, Hsinchu (TW); Jiun Yi Wu, Zhongli (TW); Chung-Shi Liu, Hsinchu (TW); and Chien-Hsun Lee, Chu-tung Town (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 1, 2023, as Appl. No. 18/363,359.
Application 18/363,359 is a division of application No. 17/205,383, filed on Mar. 18, 2021.
Claims priority of provisional application 63/127,299, filed on Dec. 18, 2020.
Prior Publication US 2024/0021467 A1, Jan. 18, 2024
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 21/60 (2006.01)
CPC H01L 21/76802 (2013.01) [H01L 21/56 (2013.01); H01L 23/31 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 2021/60022 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
a core substrate electrically connected to respective first sides of interconnect structures of a plurality of interconnect structures, wherein each interconnect structure of the plurality of interconnect structures is at least partially surrounded by an encapsulant, wherein each interconnect structure of the plurality of interconnect structures respectively comprises:
a redistribution structure;
a through via on the redistribution structure;
a molding material on the redistribution structure; and
an integrated device over the redistribution structure, wherein the molding material separates the integrated device from the redistribution structure; and
a plurality of semiconductor devices electrically connected to respective second sides of the interconnect structures of the plurality of interconnect structures, wherein the second side is opposite the first side.