US 12,362,227 B2
Method for improving profile of interconnect structure
Chun-Neng Lin, Hsinchu (TW); Jian-Jou Lian, Hsinchu (TW); and Chieh-Wei Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 16, 2022, as Appl. No. 17/841,901.
Prior Publication US 2023/0411206 A1, Dec. 21, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H10D 30/01 (2025.01)
CPC H01L 21/76802 (2013.01) [H01L 21/31111 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H10D 30/0241 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising:
forming a patterned dielectric layer over a substrate, the patterned dielectric layer including an interconnect opening having a sidewall surface and a bottom surface; and
forming a doped film by an opening-adjustment process, the doped film being disposed on the patterned dielectric layer and extending into the interconnect opening to cover an upper portion of the sidewall surface, so as to adjust a profile of the interconnect opening,
wherein the opening-adjustment process includes:
forming a first film and a second film using a deposition material such that the first film is disposed on an upper surface of the patterned dielectric layer and extends into the interconnect opening to cover the upper portion of the sidewall surface of the interconnect opening and such that the second film is disposed on the bottom surface of the interconnect opening;
implanting a dopant into the first film by an implantation process so as to form the first film into the doped film which has an etch selectivity different from an etch selectivity of the second film; and
removing the second film using a selective etching process.