US 12,362,224 B2
Semiconductor device and manufacturing method thereof
Kuo-Cheng Ching, Hsinchu County (TW); Kuan-Lun Cheng, Hsinchu (TW); Chih-Hao Wang, Hsinchu County (TW); Keng-Chu Lin, Pingtung County (TW); and Shi-Ning Ju, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Dec. 5, 2022, as Appl. No. 18/075,325.
Application 18/075,325 is a continuation of application No. 17/200,226, filed on Mar. 12, 2021, granted, now 11,522,074.
Application 17/200,226 is a continuation of application No. 16/714,532, filed on Dec. 13, 2019, granted, now 10,950,714, issued on Mar. 16, 2021.
Application 16/714,532 is a continuation of application No. 15/883,684, filed on Jan. 30, 2018, granted, now 10,510,874, issued on Dec. 17, 2019.
Claims priority of provisional application 62/592,852, filed on Nov. 30, 2017.
Prior Publication US 2023/0109238 A1, Apr. 6, 2023
Int. Cl. H10D 62/10 (2025.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H01L 21/76229 (2013.01) [H01L 21/0228 (2013.01); H10D 62/115 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H01L 21/02126 (2013.01); H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a semiconductor fin upwardly extending from a substrate;
a doped dielectric fin upwardly extending above the substrate, wherein the doped dielectric fin is doped with a first impurity;
a shallow trench isolation (STI) oxide laterally surrounding a lower portion of the semiconductor fin and a lower portion of the doped dielectric fin;
a gate structure extending across the semiconductor fin and the doped dielectric fin; and
source/drain regions on the semiconductor fin and at opposite sides of the gate structure.