US 12,362,223 B2
Semiconductor structure, fabrication method and three-dimensional memory
Teng Huang, Wuhan (CN); Ziqun Hua, Wuhan (CN); Yanwei Shi, Wuhan (CN); and Lan Yao, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jul. 5, 2022, as Appl. No. 17/857,965.
Application 17/857,965 is a continuation of application No. PCT/CN2021/115613, filed on Aug. 31, 2021.
Prior Publication US 2023/0067454 A1, Mar. 2, 2023
Int. Cl. H01L 21/762 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H10B 41/40 (2023.01); H10B 43/40 (2023.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H01L 21/76224 (2013.01) [H01L 21/30604 (2013.01); H01L 21/31144 (2013.01); H01L 21/76859 (2013.01); H10B 41/40 (2023.02); H10B 43/40 (2023.02); H10D 84/0188 (2025.01); H10D 84/038 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate including a first device region and a second device region;
forming a plurality of first recesses in the first device region and a second recess in the second device region, the first recesses and the second recess being formed simultaneously;
forming a first isolation trench in the first device region at a position different from the plurality of first recesses to separate adjacent the plurality of first recesses; and
forming a second isolation trench in the second device region at a position of the second recess.