US 12,362,192 B2
Method for manufacturing semiconductor structure, and semiconductor structure
Yexiao Yu, Hefei (CN); Zhongming Liu, Hefei (CN); Xinman Cao, Hefei (CN); Jia Fang, Hefei (CN); and Jiayun Zhang, Hefei (CN)
Assigned to CHANGXI MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/603,320
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Jul. 20, 2021, PCT No. PCT/CN2021/107452
§ 371(c)(1), (2) Date Oct. 12, 2021,
PCT Pub. No. WO2022/205687, PCT Pub. Date Oct. 6, 2022.
Claims priority of application No. 202110348261.2 (CN), filed on Mar. 31, 2021.
Prior Publication US 2023/0197461 A1, Jun. 22, 2023
Int. Cl. H01L 21/308 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/3083 (2013.01) [H01L 21/76877 (2013.01); H10B 12/482 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, the substrate comprising a plurality of active regions;
providing a first mask, the first mask comprising a plurality of first mask strips extending in a first direction, the plurality of first mask strips being parallel to one another;
using the first mask as a mask, etching the substrate blocked by the first mask strips, so as to form a plurality of first grooves in the substrate;
providing a second mask, the second mask comprising a plurality of second mask strips extending in a second direction, the plurality of second mask strips being parallel to one another, and the first direction intersecting with the second direction;
using the second mask as a mask, etching the substrate blocked by the second mask strips, so as to form a plurality of second grooves in the substrate, wherein regions, of the substrate, where the first grooves and the second grooves are located form bit line grooves, and the bit line grooves expose a part of the active regions; and
forming a conductive layer in each of the bit line grooves;
wherein after forming the conductive layer in each of the bit line grooves, the method further comprises:
forming a first initial dielectric layer on the substrate;
forming a second transfer pattern layer having a pattern on the first initial dielectric layer; and
using the second transfer pattern layer as a mask, etching the first initial dielectric layer, the first initial dielectric layer reserved forming first dielectric layers, each of the first dielectric layers and the conductive layer constituting a bit line; wherein
forming the second transfer pattern layer having the pattern on the first dielectric layer comprises:
providing a third mask, the third mask comprising a plurality of third mask strips arranged at intervals; and
using the third mask as a mask, etching the second transfer pattern layer, so as to pattern the second transfer pattern layer;
using the second transfer pattern layer as the mask, etching the first initial dielectric layer so as to form the bit line comprises:
the projection shape of the bit line is a fold line structure, and the bit line includes a plurality of first bit line structures extending in the second direction and a plurality of second bit line structures extending in the first direction, wherein each of the plurality of first bit line structures and each of the plurality of second bit line structures are arranged alternately, a bit line contact structure is provided at a connection position of each of the plurality of first bit line structures and each of the plurality of second bit line structures, the bit line contact structure is connected to the active regions, and an isolation structure is provided in a region enclosed by adjacent each of the plurality of first bit line structures and each of the plurality of second bit line structures.
 
14. A semiconductor structure, the semiconductor structure being manufactured by the method according to claim 1, wherein
the semiconductor structure comprises a substrate and bit lines, wherein the substrate is internally provided with a plurality of active regions, each of the bit lines comprises a conductive layer and a first dielectric layer, the conductive layer is provided in the substrate, and the first dielectric layer is located on the conductive layer;
wherein the projection shape of each of the bit lines is a fold line structure, and each of the bit lines included a plurality of first bit line structures extending in a second direction and a plurality of second bit line structures extending in a first direction, wherein each of the plurality of first bit line structures and each of the plurality of second bit line structures are arranged alternately, a bit line contact structure is provided at a connection position of each of the plurality of first bit line structures and each of the plurality of second bit line structures, the bit line contact structure is connected to the active regions, and an isolation structure is provided in a region enclosed by adjacent each of the plurality of first bit line structures and each of the plurality of second bit line structures.